`timescale 1ns/100ps

module IRAM 
(
	input   wire    [11:0]  address,
	input   wire            clk,
	output  reg     [31:0]  q
);

    reg [31:0]BRAM[4095:0];

    initial begin
        $readmemh("hex.txt",BRAM);
        #5 q <= 0;
    end

    always@(posedge clk)begin
        q <= BRAM[address];
    end

endmodule